Implementation of UART with BIST Technique in System-on- Chip (SOC)

In today’s life the most Manufacturing processes are extremely complex, including manufacturers to consider testability as a requirement to assure the reliability and the functionality of each of their designed circuits. One of the most popular test techniques is called Built-In-Self-Test (BIST). A Universal Asynchronous Receiver and Transmitter (UART) with BIST capability has the objectives of testing the UART on chip itself and no external devices are required to perform the test. This paper focuses on the VERILOG implementation of UART with BIST capability using SOC technology. This paper presents the architecture of UART with BIST which tests the UART for its correct ability. The whole design is simulated in cadence IUS and synthesized using RTL compiler and implemented on SOC encounter. Keywords-UART, BIST, SOC DFT, BRG, ATE.